Portfolio

Hardware Architecture: Designed a custom 32-bit Instruction Set Architecture (ISA) leveraging RISC-V and ARM paradigms. Implemented the CPU microarchitecture in SystemVerilog, targeting deployment on FPGA hardware with planned MMIO-based VGA output.

Custom Toolchain: Developed a full-featured assembler supporting pseudo-instructions and memory directives, alongside a custom "C--" compiler engineered to translate complex C-like syntax directly into native SAM32 assembly.

Interactive Web Emulator: Ported the C/C++ emulation backend to the browser via WebAssembly (Emscripten). Built a robust Dear ImGui graphical debugger featuring time-travel execution stepping, dynamic RAM/register watchlists, and an integrated LST assembly viewer for cycle-accurate state inspection.

Memory Subsystems: Employs a Bitmap Physical Memory Manager tracking 4KiB frames. The Virtual Memory Manager abstracts x86_64 page tables, explicitly unmapping the Null Page (0x0) to force hardware traps on null dereferences. Integrates a linked_list_allocator mapped at 0x4444_4444_0000 with an initial 32MB capacity.

Interrupt Handling: Configures the Interrupt Descriptor Table (IDT) and an Interrupt Stack Table (IST) for Double Faults (DOUBLE_FAULT_IST_INDEX), ensuring exceptions execute on a good stack footprint to prevent triple faults.

Syscall Architecture: Bypasses generic int 0x80 traps by updating EFER flags to enable native syscall instructions. Configures Star, LStar, and SFMask MSRs for high-speed context switching into kernel routines.

Userspace & Storage: Features an ELF loader that parses Type::Load segments, zero-fills BSS boundaries, and explicitly drops privilege to Ring 3 via an iretq instruction. Implements an ATA PIO driver executing bare port I/O, coupled with a scratch-written FAT32 translation layer resolving cluster offsets over raw ATA sectors.

Fetch-Decode-Execute: The clock loop fetches 32-bit instructions (Little-Endian) from the simulated memory bus. Operands (opcode, rd, funct3, rs1, rs2, funct7) are unpacked via bitwise masking, and immediates are dynamically sign-extended based on instruction formats (I, S, B, U, J).

Memory Model & MMIO: Memory accesses are restricted by rigorous bounds-checking. Memory-Mapped I/O (MMIO) is implemented by intercepting store8 calls to the UART0_ADDR (0x10000000), routing character outputs directly to the host terminal to bypass conventional memory modification.

Control Flow: Branch and jump instructions intelligently override the isolated Program Counter (pc) register, adjusting dynamically to accommodate the standard +4 byte cycle increment during the retirement phase.

Dynamics Control: Tuned 6-DOF Proportional-Integral-Derivative (PID) algorithms to stabilize roll, pitch, and yaw. Diagnosed real-world instability by analyzing black-box flight logs to isolate high-frequency IMU sensor noise, tuning the derivative dampening to prevent hardware overcorrection caused by wind shear.

Sensor Fusion: Integrated a neural network to fuse real-time telemetry with optical camera tracking, facilitating dynamic setpoint generation for autonomous targeting.

Low-Level Operations: Developed a custom boot sector and initialized a Physical Memory Manager and heap allocator directly from hardware mappings. Model weights are statically mapped into memory, maximizing inference pipeline throughput.

Direct Hardware Visualization: Neural activations and confidence classifications are visualized by executing direct memory-mapped I/O manipulation of the VGA hardware registers (0xB8000), bypassing standard rendering abstractions entirely.

Streamlined Userland & Init: Replaces the conventional glibc/GNU Coreutils/systemd stack with musl libc, busybox, and the runit init scheme. Utilizes the Limine bootloader and dash shell to drastically reduce the baseline memory footprint and boot latency, consciously trading edge-case compatibility for raw execution speed.

Git-Driven Package Architecture: Architected a custom, high-performance package manager natively in Rust. Leverages a decentralized Git repository tracking system as the definitive package index, facilitating deterministic dependency resolution, low-overhead version control, and reproducible system builds.

Simulation Pipeline: Built reproducible agent loop on Catanatron framework with full per-turn JSON game-state serialization (board, resources, legal actions, victory points), automated legal-action validation (up to 3 re-prompts), and deterministic board seeding for exact reproducibility.

Memory Implementations: Stateless (current state only); Recurrent (last 5 turn summaries prepended); RAG (top-3 semantic retrieval + latest grand strategy via all-MiniLM-L6-v2 embeddings stored in ChromaDB); all conditions injected identical full game state JSON at every turn with fixed temperature 0.15 on GPT OSS 120B via Groq API.

Analysis & Evaluation Framework: Embedded strategy probes every 10 turns for pairwise cosine similarity and trajectory analysis; LLM-as-judge scoring pipeline (GPT-5.1) on 5-point action-alignment rubric; full statistical suite (one-way ANOVA, Tukey's HSD, chi-square) in SciPy/Statsmodels with effect sizes; all data logged to SQLite with turn summaries, embeddings, and outcomes.

Research Output: Authored complete AP Research paper (April 2025) presenting null results (no significant differences across conditions on persistence, alignment, or win rate) and detailed limitations/discussion on prompt engineering, retrieval quality, and state informativeness; framework published as open-source reproducible benchmark for agentic LLM memory research.

Hardware Acceleration: Utilizes the wgpu graphics API to interface directly with Vulkan, Metal, and DirectX backends, maximizing matrix transformation and rendering throughput.

Cross-Compilation Target: Successfully ported to the browser environment via wasm-pack utilizing the WebGPU API, maintaining native performance parity for variable time-step physics calculations without altering the core Rust logic.

Cryptographic Pipeline: Authentication employs GPU-resistant Argon2 hashing. Files undergo symmetric client-side encryption using AES-GCM-256 with encryption keys derived via PBKDF2 (100,000 iterations) directly in the browser via the Web Crypto API.

Access Control & Isolation: Implements strict tenant isolation using Ed25519-signed JSON Web Tokens (JWTs). Blob operations restrict I/O strictly to validated UUID scopes enforced by the Axum routing middleware and SQLite schema.

Kinematic Engine & Integration: Models major celestial bodies and vehicles in 3D space. Computes pairwise Newtonian gravitational forces and employs velocity-form Störmer-Verlet integration to stably advance positional and velocity state vectors, mitigating the orbital drift common in basic Euler methods.

Deterministic Mission Architecture: Implements mission-specific aerodynamic phases including thrust staging, atmospheric drag, and guided reentry anchor points. Pre-computes and samples physics frames iteratively, completely decoupling the core simulation tick from the Raylib GUI rendering loop to ensure architectural simplicity and visual stability.

Hardware Optimization & Quantization: Engineered the inference pipeline to operate entirely on a single NVIDIA RTX 3070 Ti. Implemented weight quantization techniques to compress the model footprint, enabling the multi-million parameter network to run smoothly within an 8GB VRAM constraint without encountering Out-Of-Memory (OOM) faults.

Minimalist Architecture: Leveraged the raw, boilerplate-free nanoGPT framework and PyTorch 2.0's torch.compile to maximize token generation throughput. The model explicitly avoids the overhead of standard HuggingFace wrappers in favor of raw matrix multiplication speed.

Behavioral Profile: Intentionally tuned for rapid, localized inference rather than complex multi-step logical reasoning. The resulting model exhibits highly entertaining and comedic output generation, serving as a functional demonstration of minimalist, low-resource LLM deployment.

Memory-First Architecture: The Axum API services incoming read requests strictly from an in-memory application state, avoiding synchronous database locks during high-traffic reads.

Buffered Persistence: Write operations (e.g., telemetry/view counts) update the memory buffer instantaneously. A background Tokio thread batches these state mutations every 30 minutes, writing simultaneously to a local authoritative SQLite database and a remote Turso/libSQL cluster for synchronization.

Administrative Security: Administrative mutation endpoints are protected via an X-Admin-Password header, enabling programmatic CI/CD interaction and headless management operations.

Core Orchestration: Single FastAPI host owns the event bus, applet lifecycle, WebSocket transport (/ws/{session_id}), and static frontend serving; configuration split between eugene.toml (non-secrets) and .env (provider/channel secrets) with TOML-driven model routing via LiteLLM.

Modular Applets & Channels: Ships with applets for email (IMAP/SMTP polling & send), CalDAV calendar, DuckDuckGo web search, sandboxed Python REPL, opt-in shell execution, weather, system monitoring, PDF extraction, scheduler, and persistent memory; channels include browser WebSocket, discord.py, and python-telegram-bot—new applets added via the applets/ directory without rebuilds.

Memory & Safety Architecture: Working memory windows + persistent SQLite conversation history; optional long-term ChromaDB vector store; high-risk tools (shell, Python REPL) disabled by default with explicit opt-in configuration; token usage tracking and conversation export built-in.

Frontend & Dev Workflow: Vite/React UI built to static/ and served directly; supports frontend auto-reload (watches sources, rebuilds, and notifies connected clients); separate eugene-termagotchi Rich/Markdown terminal client for local testing.

Parallel Execution: Offloads highly parallelized tensor mathematics to dedicated Web Workers, ensuring the React frontend maintains responsive 60fps rendering during compute-heavy epochs.

Dynamic Visualization: Parses network layers (Dense, Conv1D, Conv2D, Flatten) to render real-time architectural topologies. Updates layer activations and weight magnitude thickness dynamically during backpropagation.

File System Router: Authoritative content is stored as flat HTML. On boot, the system recursively globs the directory tree to build a fast slugs.json navigational tree, resolving hierarchy and parent-child relationships dynamically.

Bidirectional Compilation: Allows authoring via Markdown, compiling seamlessly into HTML. Edits trigger an html-to-markdown reverse-engineering phase, maintaining HTML as the pure source of truth.

Security Constraints: Integrates werkzeug.security.safe_join to enforce sandboxed boundary limits on slug fetching, effectively removing path traversal vulnerabilities.