A collection of technical projects, systems architecture, and experimental code. Built with a focus on performance, scalability, and precision engineering.
Conducted a 90-trial quantitative experimental study comparing Stateless, Recurrent, and Retrieval-Augmented Generation memory architectures for LLM agents in a full Catan simulation.
VIEW DETAILS arrow_forwardEngineered real-time flight control logic for a custom Vertical Take-Off and Landing aircraft, mitigating the 'Sim-to-Real' gap in unstable aerodynamic environments.
VIEW DETAILS arrow_forwardA database-free Content Management System optimized for minimal operational overhead, utilizing an aggressive in-memory mapping cache instead of SQL.
VIEW DETAILS arrow_forwardA single-process, extensible personal AI assistant that unifies modular applets, multi-channel adapters, memory orchestration, and event-driven routing into one lightweight runtime.
VIEW DETAILS arrow_forwardA lightweight, first-principles 3D physics engine and interactive sandbox engineered to simulate orbital mechanics and accurately model the Artemis II mission trajectory.
VIEW DETAILS arrow_forwardA lightweight, autoregressive Transformer language model based on Andrej Karpathy's nanoGPT architecture, engineered specifically for local consumer-hardware execution and highly stylized text generation.
VIEW DETAILS arrow_forwardA freestanding 32-bit protected mode unikernel engineered explicitly for Feed-Forward Neural Network inference without an underlying operating system.
VIEW DETAILS arrow_forwardAn ultra-lightweight, from-scratch Linux distribution engineered to minimize system overhead by systematically replacing standard GNU/Linux bloat with highly optimized alternatives.
VIEW DETAILS arrow_forwardAn interactive, browser-based Observational System for Configuring & Analyzing Real-time neural networks (OSCAR).
VIEW DETAILS arrow_forwardA high-performance kinematic simulation engine computing velocity, acceleration vectors, and collision damping coefficients for N-particle systems.
VIEW DETAILS arrow_forwardSimulates a single-cycle scalar processor conforming strictly to the RISC-V 32-bit Integer base instruction set, modeling CPU state and flat-memory hardware constraints at the byte level.
VIEW DETAILS arrow_forwardA fully custom, ground-up 32-bit RISC computer architecture complete with a dedicated instruction set, custom software toolchain, and an interactive web-based emulator.
VIEW DETAILS arrow_forwardA latency-optimized Content Delivery platform utilizing an asynchronous, dual-layer persistence model to achieve <1ms read latency.
VIEW DETAILS arrow_forwardA bare-metal, 64-bit operating system kernel implementing strict hardware isolation, virtual memory management, and process scheduling without reliance on a standard library.
VIEW DETAILS arrow_forwardArchitected a 'Blind Store' multi-user filesystem based on the Bucket Model. The backend operates exclusively on opaque, pre-encrypted binary blobs, ensuring zero-knowledge storage.
VIEW DETAILS arrow_forward